1 1 1/12/01 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. TP5335 advanced dmos technology these enhancement-mode (normally-off) transistors utilize a vertical dmos structure and supertex? well-proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertex? vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. note: see package outline section for dimensions. package options features free from secondary breakdown low power drive requirement ease of paralleling low c iss and fast switching speeds excellent thermal stability integral source-drain diode high input impedance and high gain complementary n- and p-channel devices applications logic level interfaces ?ideal for ttl and cmos solid state relays analog switches power management telecom switches t o-236ab (sot-23) top view gate source drain p-channel enhancement-mode v ertical dmos fets low threshold absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 c to +150 c soldering temperature* 300 c * distance of 1.6 mm from case for 10 seconds. product objective specification bv dss /r ds(on) v gs(th) bv dgs (max) (max) to-236ab* wafer -350v 30 ? -2.4v TP5335k1 TP5335nw *same as sot-23. all units shipped on 3,000 piece carrier tape reels. ordering information order number/package product marking for sot-23 where *=2-week alpha date code p3s ?
2 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 1 1/12/01 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited. 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v switching waveforms and test circuit symbol parameter min typ max unit conditions bv dss drain-to-source breakdown voltage -350 v v gs = 0v, i d = -100 a v gs(th) gate threshold voltage -1.0 -2.4 v v gs = v ds , i d = -1.0ma ? v gs(th) change in v gs(th) with temperature 4.5 mv/ cv gs = v ds, i d = -1.0ma i gss gate body leakage -100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current -10 av gs = 0v, v ds = max rating -1.0 ma v gs = 0v, v ds = 0.8 max rating t a = 125 c -5.0 na v gs = 0v, v ds = -330v i d(on) on-state drain current -200 ma v gs = -4.5v, v ds = -25v -400 v gs = -10v, v ds = -25v r ds(on) 75 ? v gs = -4.5v, i d = -150ma 30 ? v gs = -10v, i d = -200ma ? r ds(on) change in r ds(on) with temperature 1.7 %/ cv gs = -10v, i d = -200ma g fs forward transconductance 125 m v ds = -25v, i d = -200ma c iss input capacitance 110 c oss common source output capacitance 60 pf c rss reverse transfer capacitance 22 t d(on) turn-on delay time 20 t r rise time 15 t d(off) turn-off delay time 25 t f fall time 25 v sd diode forward voltage drop -1.8 v v gs = 0v, i sd = -200ma t rr reverse recovery time 800 ns v gs = 0v, i sd = -200ma notes: 1. all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. electrical characteristics (@ 25 c unless otherwise specified) static drain-to-source on-state resistance v gs = 0v, v ds = -25v f = 1 mhz v dd = -25v ns i d = -150ma r gen = 25 ? ? package i d (continuous)* i d (pulsed) power dissipation jc ja i dr *i drm @ t a = 25 c c/w c/w sot-23 -85ma -400ma 0.36w 200 350 -85ma -400ma * i d (continuous) is limited by max rated t j . thermal characteristics TP5335
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